Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
AC Timing Specifications
OV
V
T
Parameter
DD
DD
J
Nominal operating conditions at 133MHz
3.3 V ± 5%
3.14 V
2.5 V ± 2.5%
2.44 V
-40°C to +85°C
+85°C
Slow case: Input Setup (T ) and Output Maximum Arrival time
IS
Fast case: Input Hold (T ) and Output Minimum Arrival time
3.46 V
2.56 V
-40°C
IH
Nominal operating conditions at 100 MHz
3.3 V ± 5%
3.14 V
2.5 V ± 5%
2.38 V
-40°C to +105°C
+105°C
Slow case: Input Setup (T ) and Output Maximum Arrival time
IS
Fast case: Input Hold (T ) and Output Minimum Arrival time
3.46 V
2.63 V
-40°C
IH
AC Input Timing Waveform
SYS_CLK
VM
T
T
IH
IS
MIN
MIN
Inputs
VM
Valid
VM (Voltage Midpoint):
SYS_CLK = 0.8V
60x bus inputs = 0.9V
All other inputs = 1.5V
Clock Timing
Notes:
1. Cycle-to-cycle
2. SYS_CLK (Min) specified for PLL_RANGE1:0 = 0b00. SYS_CLK (Max) specified for PLL_RANGE1:0 = 0b11.
Parameter
SYS_CLK clock input frequency
SYS_CLK pulse width
SYS_CLK jitter
Min
50
1
Max
133
–
Units
MHz
ns
Notes
–
± 0.15
4
ns
1
SYS_CLK slew rate
1
V/ns
MHz
%
PCI_CLK frequency
TBD
40
40
–
33.3
60
PCI_CLK duty cycle
PCG_CLK duty cycle
PCG_CLK jitter
60
%
TBD
ns
47
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