Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
I/O Specifications—133 MHz (Part 1 of 2)
Notes:
1. Output Valid from SYS_CLK
2. Output Hold from SYS_CLK
3. All inputs are referenced to the rising edge of SYS_CLK.
Input (ns)
Output (ns)
Valid
Hold
Signal
Notes
Setup
Hold
Load
(pf)
Load
(pf)
(T min)
(T min)
IS
IH
Max
Min
60x Bus Interface
SYS_ADDR0:31
SYS_ADDRP0:3
SYS_DATA0:63
SYS_DATP0:7
SYS_ARTRY
SYS_SHD
2.7
2.3
0
5
30
30
0.2
0.3
6
6
0.2
4.5
4.2
2.2
0.1
0
3.9
4.3
30
30
0.4
0.3
6
6
SYS_TA
3.1
0
4.3
30
0.3
6
SYS_TEA
SYS_TBE
nana4.3
1.8
30
0.3
6
SYS_TBST
0
0.1
0
4.3
4.3
4.3
4.3
30
30
30
30
0.3
0.3
0.3
0.3
6
6
6
6
SYS_TSIZ0:2
SYS_TT0:4
2.3
3.7
SYS_TS
3.7
0
SYS_L2_HIT
SYS_BR0:3
SYS_AACK
4.2
0.1
0
nananana
nananana
0.4
3.7
nana3.9
30
15
30
6
6
6
SYS_BG0:3
SYS_DBG0:3
SYS_GBL
nana 5
0.5
0.3
nana4.3
SYS_MACHK0:1
SYS_HRESET0:1
SYS_SRESET0:1
CHKSTOP
nana4.8
nana6.4
25
25
0.6
1.6
5
5
SDRAM Interface
MDATA00:71
SDCS0:11
1.78
0.5
4.3
1
15
0.5
5
1, 2
nana4.4
nana4.4
30
30
15
15
1,
1,
2
2
SDCKE0:9
1
SDRAS0:1
SDCAS0:1
nana7.9
70
1,
2
WE0:1
MADDR13:1
MADDR0_ODD
MADDR0_EVEN
BS1:0
nana7.1
nana 5
30
35
0.5
0.5
10
10
1,
1,
2
2
MUX_CLKEN1B
MUX_CLKEN2B
MUX_CLKENA1
MUX_CLKENA2
MUX_OEA
nana4.8
nana4.7
nana 5
35
35
35
35
35
0.5
0.5
0.5
0.5
1
10
10
10
10
10
1,
1,
1,
1,
1,
2
2
2
2
2
MUX_OEB
nana5.2
nana5.4
MUX_SEL
48
IBM [ IBM ]
