IBM PowerPC 403GCX
DRAM Read-Write-Read, One Wait
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SysClk
A11:29
Pre-
Charge
Pre-
Charge
Pre-
Charge
CAS
RAS
CAS
CAS
RAS
CAS
CAS
RAS
CAS
Row1
Column2
Column1
Row2
Row3
Column3
AMuxCAS
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
Data2
Data1
Data3
D0:31
Error
?
Error
?
Error
?
BusError
Bank Register Bit Settings
Bus Ext RAS-to- Refresh Page
Width Mux
First
Burst
Prechg Refresh Refresh
SLF ERM
CAS
Mode
Mode Access Access Cycles
RAS
Rate
Bit 13 Bit 14 Bits Bit 17 Bit 18
15:16
Bit 19
Bit 20
Bits
21:22
Bits
23:24
Bit 25
0
Bit 26
Bits
27:30
0 or 1
0
xx
x
0
0
0
01
xx
x
xxxx
Notes:
1. If internal mux mode is used, address bits A11:29 represent address bits described in Table 22 on page 37.
2. During internal mux mode access, A6:10 retain their unmultiplexed values.
3. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles.
4. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode.
5. WBE0:1 are always ones during DRAM transfers.
48
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