IBM PowerPC 403GCX
DRAM Three-state - Refresh request before and after HoldAck
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Cycle
SysClk
A6:29
WBE2/A30
WBE3/A31
HoldReq
HoldAck
RAS0:3
F
E
F
F
D
F
F
CAS0:3
F
0
F
F
0
DramWE,
DramOE,
R/W,
OE/XSize1,
EOT3/TC3/XSize0,
WBE0:3
Bank 4 refresh request
gets in just before
HoldAck
External master has
control of bus;
refreshes held off until
out of HoldAck
Bank 5 refresh counter
expired while in
HoldAck. Refresh of
bank as soon as out of
HoldAck
Bank Register Bit Settings
Bus Ext RAS-to- Refresh Page
Width Mux
10
First
Burst
Prechg Refresh Refresh
SLF ERM
CAS
Mode
Mode Access Access Cycles
RAS
Rate
x
x
0
x
0
x
x
x
x
0
xxxx
Note:
1. IOCR[EDT] is set.
49
IBM [ IBM ]
