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IBM11N1645LB-70J 参数 Datasheet PDF下载

IBM11N1645LB-70J图片预览
型号: IBM11N1645LB-70J
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 1MX64, 70ns, CMOS, PDMA168]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 344 K
品牌: IBM [ IBM ]
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IBM11N1645L  
IBM11N1735Q  
1M x 64/72 DRAM Module  
AC Characteristics (TA = 0 to +70°C, VCC = 3.3V ± 0.3V)  
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and  
VIL.  
2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is  
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh  
cycles is required..  
3. AC measurements assume tT = 2ns.  
.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)  
-60  
-6R  
-70  
Symbol  
Parameter  
Unit  
Notes  
Min  
104  
40  
10  
60  
10  
0
Max  
Min  
104  
40  
10  
60  
10  
0
Max  
Min  
124  
50  
10  
70  
12  
0
Max  
tRC  
tRP  
Random Read or Write Cycle Time  
RAS Precharge Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCP  
CAS Precharge Time  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tODD  
tDZO  
tDZC  
tT  
RAS Pulse Width  
10K  
10K  
10K  
10K  
10K  
10K  
CAS Pulse Width  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
Column Address Hold Time  
RAS to CAS Delay Time  
RAS to Column Address Delay Time  
RAS Hold Time  
10  
0
10  
0
10  
0
10  
14  
12  
10  
50  
5
10  
14  
12  
10  
50  
5
10  
14  
12  
12  
55  
5
45  
30  
43  
30  
50  
35  
1
2
CAS Hold Time  
CAS to RAS Precharge Time  
OE to DIN Delay Time  
15  
0
15  
0
15  
0
3
4
4
OE Delay Time from DIN  
CAS Delay Time from DIN  
Transition Time (Rise and Fall)  
0
0
0
2
30  
2
30  
2
30  
1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If  
tRCD is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.  
2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If  
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.  
3. Either tCDD or tODD must be satisfied.  
4. Either tDZC or tDZO must be satisfied.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
50H8035  
SA14-4630-02  
Revised 5/96  
Page 8 of 33  
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