IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
Refresh Cycle
-60
-6R
-70
Symbol
Parameter
Unit
Notes
Min
10
Max
—
Min
10
Max
—
Min
10
Max
—
CAS Hold Time
tCHR
tCSR
tWRP
tWRH
ns
ns
ns
ns
(CAS before RAS Refresh Cycle)
CAS Setup Time
5
—
—
—
5
—
—
—
5
—
—
—
(CAS before RAS Refresh Cycle)
WE Setup Time
10
10
10
10
10
10
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Refresh Cycle)
tRPC
tREF
RAS Precharge to CAS Hold Time
Refresh Period
5
—
5
—
5
—
ns
—
16
—
16
—
16
ms
1
1. 1024 refreshes are required every 16ms.
Presence Detect Read and Write Cycle
Symbol
fSCL
Parameter
Min
Max
100
100
3.5
Unit
Notes
SCL Clock Frequency
kHZ
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
TI
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
tAA
0.3
4.7
4.0
4.7
4.0
4.7
0
tBUF
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
Clock High Period
Start Condition Setup Time(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
250
SDA and SCL Rise Time
1
tf
SDA and SCL Fall Time
300
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
4.7
300
tWR
Write Cycle Time
15
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 12 of 33
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