IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
Truth Table
Row
Address
Column
Address
Function
RAS
CAS
WE
OE
DQx
H→X
L
Standby
Read
H
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
X
High Impedance
Valid Data Out
Valid Data In
Row
Row
Row
Row
Row
N/A
Col
Early-Write
Late-Write
RMW
L
L
X
Col
H→L
H→L
L
H
Col
Valid Data In
L→H
L
Col
Valid Data In/Out
Valid Data Out
Valid Data Out
Valid Data In
H→L
H→L
H→L
H→L
H→L
H→L
EDO Page Mode - Read 1st Cycle
Subsequent Cycles
H
H
L
L
Col
Col
EDO Page Mode - Write 1st Cycle
Subsequent Cycles
L
X
Row
N/A
Col
L
X
Col
Valid Data In
H→L
H→L
L→H
L→H
EDO Page Mode - RMW 1st Cycle
Subsequent Cycles
Row
N/A
Col
Valid Data In/Out
Valid Data In/Out
Col
L
H
L
L
X
H
H
X
X
L
Row
X
N/A
X
High Impedance
High Impedance
Data Out
RAS-Only Refresh
H→L
CAS-Before-RAS Refresh
L→H→L
Read
Write
Row
Col
Hidden Refresh
Self Refresh
L→H→L
H→L
L
L
H
H
X
X
Row
X
Col
X
Data In
High Impedance
Serial Presence Detect
SPD Entry
Binary
Bit4
SPD Entry
Value
Hex
Description
Number of SPD Bytes
Byte #
Bit 7
Bit 6
Bit5
Bit3
0
Bit2
0
Bit1
0
Bit0
0
0
1
2
3
4
5
128
256
EDO
10
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
80
08
02
0A
0A
01
Total # Bytes in Serial PD
Memory Type
1
0
0
0
0
0
1
0
# of Row Addresses
# of Column Addresses
# of DIMM Banks
1
0
1
0
10
1
0
1
0
1
0
0
0
1
x64
x72
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
40
48
Module Data Width
6
Module Data Width (Cont.)
Module Interface Levels
7
8
0
LVTTL
60
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
00
01
3C
46
0F
11
14
60ns
70ns
15ns
17ns
20ns
x64
RAS Access
9
70
15
CAS Access
10
11
17
20
None
ECC
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
00
02
Dimm Config(Error Det/Corr.)
x72
Refresh Rate/Type
12
13
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Normal 15.6 µs
x16
00
10
00
04
Primary DRAM Organization
x64
x72
Undefined
x4
14
Secondary DRAM Organization
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 5 of 33
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