H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
IDD0
Conditions
Units
t
t
t
t
t
t
Operating one bank active-precharge current; CK = CK(IDD), RC = RC(IDD), RAS = RAS
min(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
ING;Data bus inputs are SWITCHING
mA
Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
t
t
t
t
t
t
t
t
= 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD = RCD(IDD); CKE is HIGH, CS
is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD1
mA
t
t
Precharge power-down current; All banks idle; CK = CK(IDD); CKE is LOW; Other control and
IDD2P
IDD2Q
IDD2N
mA
mA
mA
address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge quiet standby current;All banks idle; CK = CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
t
t
Precharge standby current; All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
mA
mA
Active power-down current; All banks open; CK = CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MR(12) = 0
Slow PDN Exit MR(12) = 1
IDD3P
IDD3N
IDD4W
t
t
t
t
t
Active standby current; All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP
t
mA
mA
= RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
= CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD4R
mA
t
t
t
Burst refresh current; CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
IDD5B
IDD6
mA
mA
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
t
t
t
t
t
t
t
t
= CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC = RC(IDD), RRD = RRD(IDD),
IDD7
t
t
mA
RCD = 1* CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Rev. 0.4 / Nov 2008
17
HYNIX [ HYNIX SEMICONDUCTOR ]
