APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
3.15 Reset
The device offers a reset feature, executed by writing FFh to the command register. If the device is in Busy state during
random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being
altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait
for the next command, and the Status Register is cleared to value E0h when WP# is high. Refer to table 16 for device
status after reset operation. If the device is already in reset state a new reset command will not be accepted by the com-
mand register. The RB# pin transitions to low for tRST after the Reset command is written. Refer to Figure 28 for further
details.
3.16 Cache Read
Cache Read can be used to increase the read operation speed, as defined in Section 3.1, which is available only within
a block. As soon as the user starts to read one page, the device automatically loads the next page into the cache register.
Serial data output may be executed while data in the memory is read into cache register, Cache Read is initiated by the
page read sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or read status register IO<6> switches to high),
two command sequences can be used to continue read cache:
- sequential read cache continue (command "31h" only): once the command is latched into the command register (see
Figure 30), device does busy for a short time (tRCBSY), during which data of the first page is transferred from the data
register to the cache register. At the end of this phase cache register data can be output by toggling RE# while the "next
"page (page address M+1) is read from the memory array into data register.
- random read cache continue (sequence "00h" <page N address> "31"): once the command is latched into the command
register (see Figure 31), device does busy for a short time (tRCBSY), during which data of the first page is transferred
from the data register to the cache register. At the end of this phase cache register data can be output by toggling RE#
while page N is read from the memory array into data register.
Subsequent pages are read by issuing additional "sequential" or "random" read cache continue command sequences.
If serial data output time of one page exceeds random access time (tR), the random access time of the next page is hidden
by data downloading of the previous page.
On the other hand, if 31h is issued prior to complete the random access to the next page, the device will stay busy as long
as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random
access to the following page.
To terminate cache read, 3Fh command should be issued (see Figure 32). This command transfer data from data reg-
ister to the cache register without issuing next page read.
During the Cache Read Operation, device doesn't allow any other command except for 31h, 3Fh, Read SR or reset (FFh).
To carry out other operations Cache read must be ended either by 3Fh command or device must be reset by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers, and the busy/ready status of the
cached read operations. More in detail:
a) the Cache-Busy status bit I/O<6> indicates when the cache register is ready to output new data.
b) the status bit I/O<5> can be used to determine when the cell reading of the current data register contents is complete.
Note:
31h and 3Fh commands reset the column counter thus when RE# is toggled to output the data of a given page, the first
output data is related to the first byte of the page (column address 00h). Random data output command can be used to
switch column address.
Rev 1.4 / OCT. 2010
21
B34416/177.179.157.84/2010-10-08 10:08
*ba53f20d-240c*
HYNIX [ HYNIX SEMICONDUCTOR ]
