APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
3.8. Multiple plane copy back Program
As for page program, device supports Multi-plane copy back program with exactly same sequence and limitations. Multi
plane copy back program must be preceded by 2 single page read for copy back command sequences (1st page must be
read from the 1st plane and 2nd page from the 2nd plane).
Multi-plane copy back cannot cross plane boundaries : the contents of the source page of one device plane can be cop-
ied only to a destination page of the same plane.
EDC check is available also for multi-plane copy back program.
Users which use "EDC check" in copy back must comply with some limitations related to data handling during one multi-
plane copy back program sequence. Please refer to Section 3.10 for details.
Also in this case, two different sequences are allowed : the traditional one (85h, first plane address 11h, 81h, second
plane address, 10h) represented in Figure 22, and ONFI 1.0 sequence (85h, first plane address 11h, 85h, second
plane address, 10h) represented in Figure 23 and Figure 24.
3.9. Special read for copy back
The device feature the "special read for copy back".
If copy back read (described in sections 3.7 and 3.8) is triggered with confirm command "36h" instead "35h", copy
back read from target page(s) will be executed with an increased internal (Vpass) voltage.
This special feature is used in order to try to recover incorrigible ECC read errors due to over-program or read disturb: it
shall be used ONLY if ECC read errors have occurred in the source page using "standard read" or "standard read for
copy back" sequences..
Excluding the copy-back read confirm command, all other features described in sections 3.7 and 3.8 for standard copy
back remain valid (including the figures referred to in those sections).
3.10. EDC operation
Error Detection Code check is a feature which be used during copy back program operation (both single and multi-
plane) to detect single bit errors occurred in the source page (s).
- In the x8 version EDC check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is
composed by 512 byte of main array and 16 bytes of spare area (see Table 8 and Table 9). The described 528 byte
area is called "EDC unit".
- In the x16 version EDC allows detection of up to 1 single bit error every 264 words, where each 264 word group is
composed by 256 words of main array and 8 words of spare area (see Table 10 and Table 11). The described 264
word area is called "EDC unit".
EDC result can be checked through specific Read EDC register command, available only during copy back program and
only for the device version supporting ECC=1. EDC register can be queried during the copy back program busy time.
(tPROG)
For "EDC check" feature to operate correctly specific conditions on data input handling apply for page program and copy
back program (single, cached, multi-plane):
Rev 1.4 / OCT. 2010
17
B34416/177.179.157.84/2010-10-08 10:08
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HYNIX [ HYNIX SEMICONDUCTOR ]
