APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
3.6. Multiple plane Block Erase
Multiple plane erase, allows parallel erase of two blocks in parallel, one per each memory plane.
Two different command sequences are allowed in these case, traditional and ONFI 1.0.
In traditional case, Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation to start.
In this case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion.
See Figure 25 for details.
As an alternative, the ONFI 1.0 multiplane command protocol can be used, with 60h erase setup followed by 1st block
address and D1h first confirm, 60h erase setup followed by 2nd block address and D0h (multiplane confirm). Between the
two block-related sequences, a short busy time tIEBSY will occur. See Table 27 and Figure 26 for details.
Address limitation required for multiple plane program applies also to multiple plane erase. Also operation progress can be
checked like in the multiple plane program through Read Status Register, or ONFI 1.0 Read Status Enhanced.
As for multiplane page program, the address of the first second page must be within the first plane (A18=0 for x8
devices, A17=0 for x16 devices) and second plane (A18 = 1 for devices, A17=1 for x16 devices), respectively.
3.7. Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an exter-
nal memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance
is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and the rest of the
block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read (without mandatory serial access) and copy back -program with the address of destina-
tion page. A read operation with "35h" command and the address of the source page moves the whole 2112byte data into
the internal data buffer. As soon as the device returns to Ready state, optional data read-out is allowed by toggling RE#
(see Figure 17), or Copy Back command (85h) with the address cycles of destination page may be written. The Program
Confirm command (10h) is required to actually begin the programming operation.
Source and Destination page in the copy back program sequence must belong to the same device plane (x8 : same A18,
x16 : same A17)
Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 18.
This device includes automatic Error Detection Code check during copy back operation, to detect single bit errors in EDC
units occurred in the source page.
More details on EDC operation, and limitation related to data input handling during one copy back program sequence are
available in section 3.10
Rev 1.4 / OCT. 2010
16
B34416/177.179.157.84/2010-10-08 10:08
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HYNIX [ HYNIX SEMICONDUCTOR ]
