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H27U4G8F2DTR-BC 参数 Datasheet PDF下载

H27U4G8F2DTR-BC图片预览
型号: H27U4G8F2DTR-BC
PDF下载: 下载PDF文件 查看货源
内容描述: 4千兆( 512M ×8位)NAND闪存 [4 Gbit (512M x 8 bit) NAND Flash]
分类和应用: 闪存
文件页数/大小: 62 页 / 1015 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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APCPCWM_4828539:WP_0000001WP_0000001  
1
H27(U_S)4G8_6F2D  
4 Gbit (512M x 8 bit) NAND Flash  
ically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system con-  
troller for other tasks. Once the program process starts, the Read Status Register commands (70h or 78h) may be  
issued to read the status register. The system controller can detect the completion of a program cycle by monitoring  
the RB# output, or the Status bit (I/O 6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset  
command are valid during programming is in progress. When the Page Program is complete, the Write Status Bit (I/O  
0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.  
The command register remains in Read Status command mode until another valid command is written to the com-  
mand register. Figure 14 and Figure 15 detail the sequence.  
The device is programmed basically by page, but it also allows multiple partial page programming of a word or consec-  
utive bytes up to 2112 (x8) or 1056 (x16) in a single page program cycle.  
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the  
number indicated in Table 27. In addition, pages must be sequentially programmed within a block.  
Users which use "EDC check" in copy back must comply with some limitations related to data handling during one  
page program sequence. Please refer to Section 3.10 for details.  
3.4. Multiple plane program  
Device supports multiple plane pone per each plane.  
A multiple plane program cycle cup to 4224bytes of data may be  
loaded into the data register, follloaded data is programmed into  
the appropriate cell. The serial dInput command (80h), followed  
by the five cycle address inputpage must be in the 1st plane  
(A<18>=0). The device supporte program operation. The Dum-  
my Page Program Confirm commmes busy for a short time (tDBSY).  
Once it has become ready againmmand must be issued, followed  
by 2nd page address (5 cycles) be in the 2nd plane (A<18>=1).  
Program Confirm command (10Figure 20 and Figure 21 de-  
scribe the sequences.  
User can check operation status mands (70h or 78h), as if it were  
a normal page program: read sty Busy time (tDBSY).  
In case of fail in any of 1st and 2owever, in order to know which  
page failed, ONFI 1.0 "read station 3.11 for further info.  
The number of consecutive parthe same page must not exceed  
the number indicated in Table 2sequentially within a block.  
3.5. Block Erase  
The Block Erase operation is done on a block basis. Block address loading is accomplished in 3 cycles initiated by an  
Erase Setup command (60h). Only addresses A18 to A29 are valid while A12 to A17 are ignored. The Erase Confirm  
command (D0h) following the block address loading initiates the internal erasing process This two-step sequence of  
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise  
conditions.  
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and  
erase-verify.  
Once the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the status  
register. The system controller can detect the completion of an erase by monitoring the RB# output, or the Status bit  
(I/O 6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while eras-  
ing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.  
Figure 19 details the sequence.  
Rev 1.4 / OCT. 2010  
15  
B34416/177.179.157.84/2010-10-08 10:08  
*ba53f20d-240c*  
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