HX6228
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical
(2)
-55 to 125°C
Units
Min
Max
TAVAVR Address Read Cycle Time
16
15
12
16
12
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
Address Access Time
25
25
Address Change to Output Invalid Time
Chip Select Access Time
3
5
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Enable Access Time
10
25
16
12
6
Chip Enable Output Enable Time
Chip Enable Output Disable Time
Output Enable Access Time
5
2
10
9
4
Output Enable Output Enable Time
Output Enable Output Disable Time
4
4
9
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent
capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to 125°C, post total dose at 25°C.
TAVAVR
ADDRESS
TAVQV
TSLQV
TAXQX
NCS
TSLQX
TSHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
TEHQX
TEHQV
TELQZ
CE
TGLQX
TGLQV
TGHQZ
NOE
(NWE = high)
6
HONEYWELL [ Honeywell ]
