HC6856
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Typical (2) SER <1E-9 (4) SER <1E-10
Symbol
Parameter
Min
Max
Min
Max
Units
TAVAVW Write Cycle Time (5)
30
25
25
20
25
0
40
35
35
30
35
0
60
55
55
50
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TWLWH Write Enable Write Pulse Width
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
0
0
0
0
0
0
5
0
10
0
10
TWHQX Write Disable to Output Enable Time
15
4
5
5
TWHWL Write Disable to Write Enable Pulse Width
5
5
TEHWH
Chip Enable to End of Write Time
25
35
55
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) SER ≤1E-10 u/b-d from -55 to 80°.
(5) TAVAVW= TWLWH + TWHWL
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
TWLQZ
TWHQX
TWHDX
DATA OUT
DATA IN
HIGH
IMPEDANCE
TDVWH
DATA VALID
TSLWH
NCS
CE
TEHWH
7
HONEYWELL [ Honeywell ]
