HI-3593
RECEIVE STATUS REGISTER
PL3
FFHAFLFFEMPTY
(Receiver 1 Read, SPI Op-code 0x90)
(Receiver 2 Read, SPI Op-code 0xB0)
0
0
6
7
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
X
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
Not used.Always reads “0”
Not used.Always reads “0”
X
PL3
This bit is set when a message is received by Priority Label filter #3
This bit is set when a message is received by Priority Label filter #2
This bit is set when a message is received by Priority Label filter #1
This bit is set when the Receive FIFO contains 32ARINC 429 messages
This bit is set when the Receive FIFO contains at least 16ARINC 429 messages
This bit is set when the Receive FIFO is empty
PL2
PL1
FFFULL
FFHALF
FFEMPTY
TRANSMIT STATUS REGISTER
(Read, SPI Op-code 0x80)
X
X
TFHATLFFEMPTY
0
0
6
0
0
0
3
7
5
4
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
X
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
Not used.Always reads “0”
X
Not used.Always reads “0”
Not used.Always reads “0”
Not used.Always reads “0”
Not used.Always reads “0”
X
X
X
TFFULL
TFHALF
TFEMPTY
This bit is set when theTransmit FIFO contains 32ARINC 429 messages
This bit is set when theTransmit FIFO contains at least 16ARINC 429 messages
This bit is set when theTransmit FIFO is empty
ACLK DIVISION REGISTER
X
DIV[3]
DIV[1]DIV[0]X
(Write, SPI Op-code 0x38)
(Read, SPI Op-code 0xD4)
0
0
6
0
0
7
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
X
X
X
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Not used.
Not used.
Not used.
4 - 1 DIV[3:0]
The value programmed in DIV[3:0] sets theACLK division ratio (see table 2)
Not used.
0
X
HOLT INTEGRATED CIRCUITS
6
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
