HT46RU66/HT46CU66
Reset
The functional unit chip reset status is shown below.
There are several ways in which a reset may occur.
Program Counter
Interrupt
000H
·
RES is reset during normal operation
Disabled
Cleared
·
Power on reset
Prescaler, Divider
·
RES is reset during a Power Down
WDT, RTC,
Time Base
Cleared. After a master reset,
the WDT starts counting
·
WDT time-out is reset during normal operation
·
WDT time-out during a Power Down
Timer/event Counter Off
A WDT time-out when the device is in the Power Down
mode differs from the other reset conditions, as it per-
forms a ²warm reset² that resets only the program coun-
ter and SP and leaves the other circuits in their original
state. Some registers remain unaffected during the
other reset conditions. Most registers are reset to their
initial condition once the reset conditions are met. By ex-
amining the PDF and TO flags, the program can distin-
guish between the different types of resets.
Input/output Ports
Stack Pointer
Input mode
Points to the top of the stack
V
D
D
V
D D
m
0 . 0 1 F
1
0
0
k
W
1
0
0
k
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES Wake-up HALT
R
E
S
R
E
S
m
0 . 1 F
0
u
0
1
1
0
u
1
u
1
1
0
k
B
a
s
i
c
H
i
-
n
o
i
s
e
R
e
s
e
t
R
e
s
e
t
m
0 . 1 F
C
i
r
c
u
i
t
C
i
r
c
u
i
t
WDT time-out during normal operation
WDT Wake-up HALT
Reset Circuit
Note: Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
Note: ²u² stands for unchanged
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem awakens from the Power Down mode or during
power up.
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
W
D
T
T
i
m
e
-
o
u
t
R
e
s
e
t
E
x
t
e
r
n
a
l
V
D
D
R
E
S
R
E
S
C
o
l
d
t
S S T
S
S
T
R
e
s
e
t
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
S
S
T
T
i
m
e
-
o
u
t
C
o
u
n
t
e
r
C
h
i
p
R
e
s
e
t
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
o
n
Reset Timing Chart
Reset Configuration
Rev. 1.20
17
October 2, 2007