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Timer/Event Counter 2
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PFD Source Option
The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/ T2PSC2~0) can be used to define the pre-scaling stages of the inter-
nal clock sources of the timer/event counter. The overflow signal of the timer/event counter can be used to generate the
PFD signal. The timer prescaler is also used as the PWM counter.
Bit No.
Label
Function
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
0
1
2
T0PSC0
T0PSC1
T0PSC2
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
3
T0E
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enables/disables the timer counting
(0=disable; 1=enable)
4
5
T0ON
¾
Unused bit, read as ²0²
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
T0M0
T0M1
TMR0C (0EH) Register
Rev. 1.20
21
October 2, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
