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HT46R12(24SOP-A) 参数 Datasheet PDF下载

HT46R12(24SOP-A)图片预览
型号: HT46R12(24SOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO24]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 45 页 / 314 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R12  
Reset  
The functional unit chip reset status are shown below.  
There are three ways in which a reset can occur:  
Program Counter  
Interrupt  
000H  
·
·
·
RES reset during normal operation  
RES reset during HALT  
Disable  
Cleared  
Prescaler, Divider  
WDT time-out reset during normal operation  
Clear. After master reset,  
WDT begins counting  
WDT  
The WDT time-out during HALT is different from other  
chip reset conditions, since it can perform a ²warm re -  
set² that resets only the program counter and SP, leav-  
ing the other circuits in their original state. Some regis-  
ters remain unchanged during other reset conditions.  
Most registers are reset to the ²initial condition² when  
the reset conditions are met. By examining the PDF and  
TO flags, the program can distinguish between different  
²chip resets².  
Timer/Event Counter Off  
PPG Timer  
Off  
PPG output  
Floating  
Input/Output Ports  
Stack Pointer  
Input mode  
Points to the top of the stack  
TO PDF  
RESET Conditions  
RES reset during power-up  
RES reset during normal operation  
RES wake-up HALT  
V
D
D
0
u
0
1
1
0
u
1
u
1
m
0 . 0 1 F *  
1
0
0
k
R
E
S
WDT time-out during normal operation  
WDT wake-up HALT  
1
0
k
m
0 . 1 F *  
Note: ²u² means unchanged  
Reset Circuit  
To guarantee that the system oscillator is started and  
stabilized, the SST (System Start-up Timer) provides an  
extra delay of 1024 system clock pulses when the sys-  
tem reset (power-up, WDT time-out or RES reset) or the  
system awakes from the HALT state.  
Note:  
²*² Make the length of the wiring, which is con-  
nected to the RES pin as short as possible, to  
avoid noise interference.  
When a system reset occurs, the SST delay is added  
during the reset period. Any wake-up from HALT will en-  
able the SST delay.  
H
A
L
T
W
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m
R
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W
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An extra option load time delay is added during a system  
reset (power-up, WDT time-out at normal mode or RES  
reset).  
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Reset Configuration  
Reset Timing Chart  
Rev. 1.20  
13  
February 24, 2006  
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