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HT45R04E 参数 Datasheet PDF下载

HT45R04E图片预览
型号: HT45R04E
PDF下载: 下载PDF文件 查看货源
内容描述: [适用于安防系列(烟感器、温感器、家用一 氧化碳测试器)等产品的 IC:HT45R04E。 工作电压:2.2V~5.5V ;工作频率:400Kz---2MHz(当fsys=455kHz时,VDD=+5V时 IDD<200uA) 1. 最多可有13 个双向输入/输出口 , 18-pin SOP 封装 2. 1 个与输入/输出口共用引脚的外部中断输入 3. 8 位可编程定时/计数器,具有溢出中断和7 级预分频器 4. 内置晶体和RC 振荡电路 5. 看门狗定时器 6. 1024×14Bits 程序存储器ROM 7. 64×8Bits 数据存储器RAM 8. 128×8Bits 数据存储器EEPROM,符合IIC通信协议(使用方法同24C01一致) 9. 具有PFD 功能,可以用来发声 10. HALT 和唤醒功能可降低功耗 11. 4 层硬件堆栈 12. 4 通道8 位解析度的A/D 转换器 13. 查表指令,表格内容字长14 位 14. 63 条指令,包含位操作指令 15. 指令执行时间为1 或2 个指令周期]
分类和应用: 晶体转换器预分频器计数器存储测试通信可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 43 页 / 2641 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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Preliminary  
HT45R04/HT45R04E  
signaled by a return instruction (RET or RETI), the pro-  
gram counter is restored to its previous value from the  
stack. After a chip reset, the SP will point to the top of the  
stack.  
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If the stack is full and a non-masked interrupt takes  
place, the interrupt request flag will be recorded but the  
acknowledge will be inhibited. When the stack pointer is  
decremented (by RET or RETI), the interrupt will be ser-  
viced. This feature prevents stack overflow allowing the  
programmer to use the structure more easily. In a similar  
case, if the stack is full and a ²CALL² is subsequently  
executed, stack overflow occurs and the first entry will  
be lost (only the most recent 4 return addresses are  
stored).  
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Data Memory - RAM  
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The data memory is designed with 85´8 bits. The data  
memory is divided into 2 functional groups: special func-  
tion registers and general purpose data memory (64´8).  
Most of them are read/write, but some are read only.  
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The special function registers include the indirect ad-  
dressing register (00H), timer/event counter  
(TMR;0DH), timer/event counter control register  
(TMRC;0EH), program counter lower-order byte regis-  
ter (PCL;06H), memory pointer register (MP;01H), ac-  
cumulator (ACC;05H), table pointer (TBLP;07H), table  
higher-order byte register (TBLH;08H), status register  
(STATUS;0AH), interrupt control register (INTC;0BH),  
timer register (TMR;0DH), timer control register  
(TMRC;0EH), I/O port data registers (PA;12H, PB;14H,  
PD;18H), I/O port control registers (PAC;13H,  
PBC;15H, PDC;19H), A/D high-byte register  
(ADRH;21H), A/D control register (ADCR;22H) and A/D  
clock setting register (ACSR;23H). The remaining  
space before the 40H is reserved for future expansion  
and reading these locations will return the result ²00H².  
The general purpose data memory, addressed from 40H  
to 7FH, is used for data and control information under in-  
struction commands.  
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All of the data memory areas can handle arithmetic,  
logic, increment, decrement and rotate operations di-  
rectly. Except for some dedicated bits, each bit in the  
data memory can be set and reset by ²SET [m].i² and  
²CLR [m].i². They are also indirectly accessible through  
memory pointer register (MP;01H).  
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RAM Mapping  
The bit 7 of MP is undefined and reading will return the  
result ²1². Any writing operation to MP will only transfer  
the lower 7-bit data to MP.  
Indirect Addressing Register  
Location 00H is an indirect addressing register that is  
not physically implemented. Any read/write operation of  
[00H] accesses the data memory pointed to by MP  
(01H). Reading location 00H itself indirectly will return  
the result 00H. Writing indirectly results in no operation.  
Accumulator  
The accumulator is closely related to ALU operations. It  
is also mapped to location 05H of the data memory and  
can carry out immediate data operations. The data  
movement between two data memory locations must  
pass through the accumulator.  
The memory pointer register MP (01H) is a 7-bit register.  
Rev. 0.00  
9
December 30, 2004  
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