GS9090 Data Sheet
A write and read pointer offset may be programmed in the
FIFO_EMPTY_OFFSET[9:0] register of the host interface. If an offset value is
programmed in this register, the FIFO_EMPTY flag will be set HIGH when the read
and write pointers of the FIFO are at the same address, and will remain HIGH until
the write pointer reaches the programmed offset. Once the pointer offset has been
exceeded, the FIFO_EMPTY flag will go LOW (see block B in Figure 3-11).
In the case where the read pointer is originally ahead of the write pointer, the
FIFO_FULL flag will be set HIGH when both pointers arrive at the same address
(see block C in Figure 3-11). The application layer can use this flag to determine
when to begin reading from the device.
A read and write pointer offset may also be programmed in the
FIFO_FULL_OFFSET[9:0] register of the host interface. If an offset value is
programmed in this register, the FIFO_FULL flag will be set HIGH when the read
and write pointers of the FIFO are at the same address, and will remain set HIGH
until the read pointer reaches the programmed offset. Once the pointer offset has
been exceeded, the FIFO_FULL flag will be cleared (see block D in Figure 3-11).
Gating the RD_CLK Using the FIFO_EMPTY Flag
Using the asynchronous FIFO_EMPTY flag to gate RD_CLK requires external
clock gating circuity to generate a clean burst clock (see Figure 3-9). An example
circuit for this application is shown in Figure 3-10.
Figure 3-9: Burst Clock
FIFO_EMPTY
SET
SET
SET
D
Q
Q
D
Q
Q
D
Q
Q
GATED
RD_CLK
CLR
CLR
CLR
RD_CLK
RD_CLK
FIFO_EMPTY
GATED
RD_CLK
Figure 3-10: Example Circuit to Gate RD_CLK Using the FIFO_EMPTY Flag
28201 - 1 July 2005
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