GS9090 Data Sheet
3.10.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the application layer sets the
FIFO_EN pin HIGH, and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 01b. By default, the FIFO_MODE[1:0] bits are set to 01b
by the device whenever the DVB_ASI pin is set HIGH (i.e. the device is in DVB-ASI
mode); however, the application layer may program the FIFO_MODE[1:0] bits as
required.
Figure 3-8 shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
Application Interface
Internal
8-bit MPEG Data
8-bit MPEG Data
WORDERR
SYNCOUT
WORDERR
SYNCOUT
FIFO
(DVB-ASI Mode)
FIFO_EMPTY
FIFO_FULL
WR_CLK
(PCLK gated with SYNCOUT)
RD_CLK
Figure 3-8: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9090's FIFO can be used for clock rate
interchange operation. The extracted 8-bit MPEG packets will be written into the
FIFO at 27MHz based on the SYNCOUT signal from the internal DVB-ASI decoder
block. The SYNCOUT and WORDERR bits are also stored in the FIFO (see Status
Signal Outputs on page 29).
When SYNCOUT goes HIGH, K28.5 stuffing characters have been detected and
no data will be written into the FIFO.
Data is read out of the FIFO by the application layer using the RD_CLK pin. In
DVB-ASI mode, the RD_RESET pin is not used.
3.10.2.1 Reading From the FIFO
The FIFO contains internal read and write pointers used to designate which spot in
the FIFO the MPEG packet will be read from or written to. These internal pointers
control the status flags FIFO_EMPTY and FIFO_FULL, which are available for
output on the multi-function output port pins, if so programmed (see Programmable
Multi-Function Outputs on page 56).
In the case where the write pointer is originally ahead of the read pointer, the
FIFO_EMPTY flag will be set HIGH when both pointers arrive at the same address
(see block A in Figure 3-11). The application layer can use this flag to determine
when to stop reading from the device.
28201 - 1 July 2005
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