GS9090 Data Sheet
A
0
0
0
0
B
Internal write
pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Application layer
read pointer
ANC_DATA
ANC_DATA
Application layer
read pointer
ANC_DATA
ANC_DATA
ANC_DATA
Internal write
pointer
1023
1023
1023
1023
ANC_DATA_SWITCH = LOW
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written
to second half of FIFO starting at adress zero. Application layer continues to
read from the first half of the FIFO.
C
D
0
0
0
0
Application layer
read pointer
Internal write
pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
%%
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Application layer
read pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Internal write
pointer
%%
1023
ANC_DATA_SWITCH = LOW
1023
1023
ANC_DATA_SWITCH = HIGH
1023
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of
FIFO starting at address zero. Application layer continues to read from second half
of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the
FIFO and go back the situation depicted in box A.
ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary
data read from second half of FIFO. Device continues to write ancillary data
to second half of FIFO.
NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit.
The bit must be toggled at a point where no extraction is occuring (i.e. the ANC signal is LOW).
Figure 3-12: Ancillary Data Extraction and Reading
28201 - 1 July 2005
53 of 70
GENNUM [ GENNUM CORPORATION ]
