GS9090 Data Sheet
3.10 Internal FIFO Operation
The GS9090 contains an internal video line-based FIFO, which can be
programmed by the application layer to work in any of the following modes:
1. Video Mode,
2. DVB-ASI Mode,
3. Ancillary Data Extraction Mode, or
4. Bypass Mode
The FIFO can be configured to one of the four modes by using the host interface
to set the FIFO_MODE[1:0] bits of the IOPROC_DISABLE register (see Table 3-14
in Error Correction and Insertion on page 43). The setting of these bits is shown in
Table 3-15. To enable the FIFO, the application layer must also set the FIFO_EN
pin HIGH. Additionally, if the FIFO is configured for video mode or ancillary data
extraction mode, the IOPROC_EN pin must be set HIGH.
The FIFO is fully asynchronous, allowing simultaneous read and write access. It
has a depth of 2048 words, which will accommodate 1 full line of SD video for both
525 and 625 standards. The FIFO is 15 bits wide: 10 bits for video data and 5 bits
for other signals, such as H, V, F, EDH_DETECT, and ANC_DETECT.
Table 3-15: FIFO Configuration Bit Settings
FIFO_MODE[1:0]
FIFO_EN
Pin Setting
IOPROC_EN
Pin Setting
FIFO Mode
Register Setting
Video Mode
00b
01b
10b
11b
HIGH
HIGH
HIGH
X
HIGH
X
DVB-ASI Mode
Ancillary Data Extraction Mode
Bypass Mode
HIGH
X
NOTE: ‘X’ signifies ‘don’t care’. The pin is ignored and may be set HIGH or LOW.
3.10.1 Video Mode
The internal FIFO is in video mode when the application layer sets the FIFO_EN
and IOPROC_EN pins HIGH, and the FIFO_MODE[1:0] bits in the
IOPROC_DISABLE register are configured to 00b. By default, the
FIFO_MODE[1:0] bits are set to 00b by the device whenever the SMPTE_BYPASS
pin is set HIGH and the DVB_ASI pin is set LOW (i.e. the device is in SMPTE
mode); however, the application layer may program the FIFO_MODE[1:0] bits as
required.
Figure 3-6 shows the input and output signals of the FIFO when it is configured for
video mode.
28201 - 1 July 2005
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GENNUM [ GENNUM CORPORATION ]
