GS9090 Data Sheet
3.10.3 Ancillary Data Extraction Mode
The internal FIFO is ancillary data extraction mode when the application layer sets
the FIFO_EN and IOPROC_EN pins HIGH, and the FIFO_MODE[1:0] bits in the
IOPROC_DISABLE register are configured to 10b.
Once the FIFO enters ancillary data extraction mode, it takes 2200 PCLKs (82us)
to initialize the FIFO before ancillary data extraction can begin.
In this mode, the FIFO is divided into two separate blocks of 1024 words each. This
allows ancillary data to be written to one side of the FIFO while the application layer
reads from the other. Thus, in each half of the FIFO, the GS9090 will write the
contents of the packets up to a maximum of 1024 8-bit words.
As described in Programmable Ancillary Data Detection on page 31, up to five
specific types of ancillary data to be extracted can be programmed in the
ANC_TYPE registers. If the ANC_TYPE registers are all set to zero, the device will
extract all types of ancillary data.
The entire packet, including the ancillary data flag (ADF), data identification (DID),
secondary data identification (SDID), data count (DC), and checksum word will be
written into the memory. The device will detect ancillary data packet DID's placed
anywhere in the video data stream, including the active picture area.
Additionally, the lines from which the packets are to be extracted from can be
programmed into the ANC_LINE_A[10:0] and ANC_LINE_B[10:0] registers,
allowing ancillary data from a maximum of two lines per frame to be extracted. If
only one line number register is programmed (with the other set to zero), ancillary
data packets will be extracted from one line per frame only. When both registers
are set to zero, the device will extract packets from all lines.
The application layer reads the extracted ancillary data through the host interface
starting at address 02Ch up to 42Bh inclusive (1024 words). This must be done
while there is a valid video signal present at the serial input and the device is locked
(LOCKED = HIGH).
3.10.3.1 Ancillary Data Extraction and Reading
To start ancillary data extraction, the ANC_PKT_EXT bit of the IOPROC_DISABLE
register must be set HIGH (see Table 3-14 in Error Correction and Insertion on
page 43). Packet extraction will begin in the following frame after this bit has been
set HIGH.
NOTE: Ancillary data extraction will not begin until 2200 PCLKs (82us) after the
device has entered into ancillary data extraction mode (FIFO_MODE[1:0] = 10b),
regardless of the setting of the ANC_PKT_EXT bit.
When the FIFO is configured for ancillary data extraction mode, setting the
IOPROC_EN pin LOW will disable packet extraction. If IOPROC_EN is LOW, the
setting of the ANC_PKT_EXT host interface bit will be ignored.
28201 - 1 July 2005
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