GS9090 Data Sheet
3.9.8.2 EDH CRC Error Correction
If the EDH_CRC_INS bit of the IOPROC_DISABLE register is set LOW, the
GS9090 will generate and insert active picture and full field CRC words into the
EDH data packets received by the device.
Additionally, when EDH_CRC_INS is LOW, the device will set the active picture
and full field CRC ‘V’ bits HIGH in the EDH packet (see EDH Flag Detection on
page 33). The AP_CRC_V and FF_CRC_V register bits will only report the
received EDH validity flags.
EDH CRC calculation ranges are described in EDH CRC Error Detection on
page 40.
NOTE: Although the GS9090 will modify and insert EDH CRC words and EDH
packet checksums, the device will only update EDH error flags when the
EDH_FLAG_UPDATE bit is set HIGH (see EDH Flag Detection on page 33).
3.9.8.3 Ancillary Data Checksum Error Correction
When ancillary data checksum error correction and insertion is enabled, the
GS9090 will generate and insert ancillary data checksums for all ancillary data
words by default. Where user specified ancillary data has been programmed into
the ANC_TYPE registers of the host interface (see Programmable Ancillary Data
Detection on page 31), only the checksums for the ancillary data programmed will
be corrected.
This feature is enabled when the ANC_CSUM_INS bit of the IOPROC_DISABLE
register is set LOW.
3.9.8.4 TRS Error Correction
When TRS error correction and insertion is enabled, the GS9090 will generate and
insert 10-bit TRS code words as required.
TRS word generation will be performed in accordance with the timing parameters
generated by the flywheel to provide an element of noise immunity. As a result,
TRS correction will only take place if the flywheel in enabled (FW_EN = HIGH).
In addition, the TRS_INS bit of the IOPROC_DISABLE register must be set LOW.
NOTE: Only H timing based errors will be corrected (see TRS Error Detection on
page 43).
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