GS9090 Data Sheet
Internal
Application Interface
10-bit Video Data
10-bit Video Data
H
H
V
V
FIFO
(Video Mode)
F
F
ANC
ANC
EDH_DETECT
EDH_DETECT
RD_RESET
RD_CLK
WR_RESET
WR_CLK (PCLK)
Figure 3-6: FIFO in Video Mode
When operating in video mode, the GS9090 will write data sequentially into the
FIFO, starting with the first active pixel in location zero of the memory. In this mode,
it is possible to use the FIFO for clock phase interchange and data alignment /
delay. The extracted H, V, and F information will also be written into the FIFO. The
H, V, and F outputs will be timed to the video data read from the FIFO by the
application interface (see HVF Timing Signal Generation on page 28).
The device will ensure write-side synchronization is maintained, according to the
extracted PCLK and flywheel timing information.
Full read-control of the FIFO is made available to the application interface such that
data will be clocked out of the FIFO on the rising edge of the externally provided
RD_CLK signal. When there is a HIGH-to-LOW transition at the RD_RESET pin
the first pixel presented to the video data bus will be the first 000 of the SAV (see
Figure 3-7). The FIFO_LD pulse may be used to control the RD_RESET pin.
NOTE: The RD_RESET pulse should not be held LOW for more than one RD_CLK
cycle.
RD_CLK
Y'CbCr DATA
RD_RESET
XYZ
3FF
000
000
Figure 3-7: RD_RESET Pulse Timing
In video mode, the ANC_DETECT output signal will be timed to the data output
from the FIFO (see Ancillary Data Detection and Indication on page 31 for more
detail).
28201 - 1 July 2005
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GENNUM [ GENNUM CORPORATION ]
