GS9090 Data Sheet
Clearing the ANC_PKT_EXT bit will not automatically disable ancillary data
extraction. To disable ancillary data extraction, switch the FIFO into bypass mode
by setting FIFO_MODE[1:0] = 11b. 2200 PCLK cycles after the device re-enters
ancillary data extraction mode, data extraction will commence immediately if
ANC_PKT_EXT is still HIGH.
The application layer can use the ANC_DETECT output flag available on the I/O
output pin (see Programmable Multi-Function Outputs on page 56) to determine
the length of the ancillary data extracted and when to begin reading the extracted
data from memory. Recall that ANC_DETECT is HIGH whenever ancillary data
has been detected.
In addition, the data count (DC) word, which is located three words after the
ancillary data flag (ADF) in the memory, can be read to determine how many valid
user data words (UDW) are present in the extracted packet (see SMPTE 291M for
more details). The DC value can then be used to preset how many address reads
must be performed to obtain only the user data words.
Ancillary data will be written into the first half of the FIFO until it is full or until the
ANC_DATA_SWITCH bit is toggled (i.e. a HIGH-to-LOW or LOW-to-HIGH
transition). If the ANC_DATA_SWITCH bit is not toggled, extracted data will not be
written into memory after the first half of the FIFO is full (see block A in
Figure 3-12).
When the ANC_DATA_SWITCH bit is toggled, new extracted data will be written
to the second half starting at address zero (see block B in Figure 3-12). The data
in the first half of the FIFO may still be read.
Once the data in the first half of the FIFO has been read, the ANC_DATA_SWITCH
may be toggled again to enable the second half of the FIFO to be read. The first
half of the FIFO will be cleared, and the device will continue to write ancillary data
to the second half of the FIFO (see block C in Figure 3-12).
If the ANC_DATA_SWITCH bit is toggled again, new extracted data will be written
to the first half starting at address zero (see block D in Figure 3-12). The data in the
second half of the FIFO may still be read.
Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and
restore the read and write pointers to the situation shown in block A. The switching
process (shown in blocks A to D in Figure 3-12) will continue with each toggle of
the ANC_DATA_SWITCH bit.
NOTE: At least 1100 PCLK cycles (41us) must pass between toggles of the
ANC_DATA_SWITCH bit. The ANC_DATA_SWITCH bit must be toggled at a point
in the video where no extraction is occurring (i.e. the ANC_DETECT signal is
LOW).
28201 - 1 July 2005
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