GS9090 Data Sheet
Table 3-14: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 00h
15-10
9
–
Not Used
–
–
0
ANC_PKT_EXT
Ancillary Packet Extraction. When the FIFO is
configured for Ancillary Data Extraction mode, the
application layer must set this bit HIGH to begin
extraction.
R/W
NOTE: Setting ANC_PKT_EXT LOW will not
automatically disable ancillary data extraction (see
Ancillary Data Extraction and Reading on page 51).
8-7
6
FIFO_MODE[1:0]
H_CONFIG
FIFO Mode: These bits control which mode the internal
FIFO is operating in (see Table 3-15)
R/W
R/W
0
0
Horizontal sync timing output configuration. Set LOW
for active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS word. See
Figure 3-3 in HVF Timing Signal Generation on
page 28.
5-4
3
Not Used.
ILLEGAL_REMAP
EDH_CRC_INS
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN pin must be set HIGH.
R/W
R/W
0
0
2
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. Set HIGH to
disable. The IOPROC_EN pin must be set HIGH.
1
0
ANC_CSUM_INS
TRS_INS
Ancillary Data Checksum insertion. Set HIGH to
disable. The IOPROC_EN pin must be set HIGH.
R/W
R/W
0
0
Timing Reference Signal Insertion. The device will
correct TRS based errors when set LOW (see TRS
Error Correction on page 45). The IOPROC_EN pin
must also be HIGH.
Set this bit HIGH to disable.
3.9.8.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the
GS9090 will remap all codes within the active picture between the values 3FCh and
3FFh to 3FBh. All codes within the active picture area between the values 00h and
03h will be re-mapped to 04h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit
values if this feature is enabled.
28201 - 1 July 2005
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