GS9090 Data Sheet
3.9.7.3 Lock Error Detection
The LOCKED pin of the GS9090 indicates the lock status of the internal reclocker
and lock detect blocks of the device. Only when the LOCKED pin is asserted HIGH
has the device correctly locked to the received data stream (see Lock Detect on
page 22).
The GS9090 will also indicate lock error to the host interface when LOCKED =
LOW by setting the LOCK_ERR bit in the ERROR_STATUS register HIGH.
3.9.7.4 Ancillary Data Checksum Error Detection
The GS9090 will calculate checksums for all received ancillary data and compare
the calculated values to the received checksum words. If a mismatch is detected,
the CS_ERR bit of the ERROR_STATUS register will be set HIGH.
Although the GS9090 will calculate and compare checksum values for all ancillary
data types by default, the host interface may program the device to check only
certain types of ancillary data checksums. This is accomplished via the
ANC_TYPE registers as described in Programmable Ancillary Data Detection on
page 31.
3.9.7.5 TRS Error Detection
TRS error flags are generated by the GS9090 when:
1. The received TRS H timing does not correspond to the internal flywheel
timing; or
2. The received TRS hamming codes are incorrect.
Both 8-bit and 10-bit SAV and EAV TRS words are checked for timing and data
integrity errors. These are flagged via the SAV_ERR and/or EAV_ERR bits of the
ERROR_STATUS register.
NOTE: H timing based TRS errors will only be generated if the FW_EN pin is set
HIGH. F & V timing errors are not detected or corrected.
3.9.8 Error Correction and Insertion
In addition to signal error detection and indication, the GS9090 may also correct
certain types of errors by inserting corrected code words, checksums, and TRS
values into the data stream. These features are only available in SMPTE mode and
the IOPROC_EN pin must be set HIGH by the application layer. Individual
correction features may be enabled or disabled by setting bits 0 to 3 in the
IOPROC_DISABLE register (Table 3-14).
All of the IOPROC_DISABLE register bits default to '0' after a device reset,
enabling all of the processing features. To disable any individual error correction
feature, the host interface must set the corresponding bit HIGH in the
IOPROC_DISABLE register.
28201 - 1 July 2005
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