Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
G4
IOPROC_EN/DIS
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• EDH CRC Error Correction (SD-only)
• ANC Data Checksum Correction
• Line-based CRC Error Correction (HD-only)
• Line Number Error Correction (HD-only)
• TRS Error Correction
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the Host Interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
G5
SMPTE_BYPASS
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in Slave mode, and
will be an output set by the device in Master mode.
Master mode (MASTER/SLAVE = HIGH)
The SMPTE_BYPASS signal will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW otherwise.
Slave mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may
be enabled in this mode.
When set LOW, the device will not support the descrambling, decoding
or word alignment of received SMPTE data. No I/O processing features
will be available.
G6
RESET_TRST
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and
to reset the JTAG test sequence.
Host mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high-impedance,
including the Serial Digital Outputs SDO and SDO.
Must be set HIGH for normal device operation.
NOTE: When in Slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG test mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
12 of 71
30572 - 8
July 2008
GENNUM [ GENNUM CORPORATION ]
