GL9701 PCI ExpressTM to PCI Bridge
6.29 Offset 74h: PCI Express Device Capabilities Register
Bits
Type
Default
Description
Max_Payload_Size Supported –512 bytes max payload size is
supported.
2:0
RO
010b
Phantom Functions Supported –No function number bits used
for Phantom Functions; device may implement all function
numbers.
4:3
5
RO
RO
RO
00b
0b
Extended Tag Field Supported –5-bit Tag field supported
Endpoint L0s Acceptable Latency –The acceptable total latency
8:6
111b that an Endpoint can withstand due to the transition from L0s state
to the L0 state is more than 4 µs.
Endpoint L1 Acceptable Latency –The acceptable latency that an
111b Endpoint can withstand due to the transition from L1 state to the
L0 state is more than 64 µs.
11:9
RO
Attention Button Present – Not supported.
Attention Indicator Present – Not supported.
Power Indicator Present – Not supported.
RsvdP
12
13
RO
RO
0b
0b
14
RO
0b
17:15
RsvdP
000b
Captured Slot Power Limit Value – In combination with the Slot
Power Limit Scale value, specifies the upper limit on power
supplied by slot. This value is set by the Set_Slot_Power_Limit
Message
25:18
27:26
RO
RO
00h
00b
Captured Slot Power Limit Scale – Specifies the scale used for
the Slot Power Limit Value. This value is set by the
Set_Slot_Power_Limit Message.
6.30 Offset 78h: PCI Express Device Control Register
Bits
Type
Default
Description
Correctable Error Reporting Enable – This bit controls
0
RW
0b
reporting of correctable errors.
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