GL9701 PCI ExpressTM to PCI Bridge
(addresses defined above) unless they are enabled for
forwarding by the defined I/O and memory address
ranges.
1– Forward VGA compatible memory and I/O addresses
(addresses defined above) from the primary interface to
the secondary interface (if the I/O Enable and Memory
Enable bits are set) independent of the I/O and memory
address ranges and independent of the ISA Enable bit.
VGA 16-bit Decode – This bit enables the bridge to provide 16-bit
decoding of VGA I/O address precluding the
decoding of alias addresses every 1 KB. This bit only has
meaning if the VGA Enable bit in this register is also set to 1,
enabling VGA I/O decoding and forwarding by the bridge.
0 – Execute 10-bit address decodes on VGA I/O
accesses.
4
RW
0b
1– Execute 16-bit address decodes on VGA I/O
accesses.
Master-Abort Mode – Controls the behavior of a bridge when it
receives a Master-Abort termination (e.g., an Unsupported Request
on PCI Express) on either interface.
0 – Do not report Master-Aborts. When a UR response is
received from PCI Express for non-posted transactions,
and when the secondary side is operating in conventional
PCI mode, return FFFF FFFFh on reads and complete I/O
writes normally. When a Master-Abort is received on the
secondary interface for posted transactions initiated from
the primary interface, no action is taken (i.e., all data is
discarded).
5
RW
0b
1 – Report UR Completions from PCI Express by signaling
Target-Abort on the secondary interface when the
secondary interface is operating in conventional PCI
mode. For posted transactions initiated from the primary
interface and Master-Aborted on the secondary interface,
the bridge must return an ERR_NONFATAL (by default)
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 46
GENESYS [ GENESYS LOGIC ]
