GL9701 PCI ExpressTM to PCI Bridge
or ERR_FATAL transaction (provided the SERR# Enable
bit is set in the Command register). The severity is
selectable only if Advanced Error Reporting is supported.
Secondary Bus Reset – Forces the assertion of RST# on the
secondary interface.
6
RW
0b
0 – Do not force the assertion of the secondary interface
RST#.
1 – Force the assertion of the secondary interface RST#.
Fast Back-to-Back Enable – Controls ability of the bridge to
generate fast back-to-back transactions to different devices on the
secondary interface.
7
8
RO
RO
0b
0b
0 – Disable generation of fast back-to-back transactions on
the secondary interface.
1 – Enable generation of fast back-to-back transactions on the
secondary interface.
Primary Discard Timer – Does not apply to PCI Express.
Secondary Discard Timer – When in conventional PCI mode,
elects the number of PCI clocks that the bridge will wait for a
master on the secondary interface to repeat a Delayed Transaction
request
9
RW
0b
0 – The Secondary Discard Timer counts 215 PCI clock
cycles.
1– The Secondary Discard Timer counts 210 PCI clock
cycles.
Discard Timer Status – This bit is set to a 1 when the Secondary
Discard Timer expires and a Delayed Completion is discarded
from a queue in the bridge.
10
11
RW
RW
0b
0b
0 – No discard timer error.
1 – Discard timer error.
Discard Timer SERR# Enable – This bit enables the bridge to
generate either an ERR_NONFATAL (by default) or
ERR_FATAL transaction on the primary interface when the
Secondary Discard Timer expires and a Delayed Transaction is
discarded from a queue in the bridge.
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