GL9701 PCI ExpressTM to PCI Bridge
0 – Disable the forwarding of SERR# from the secondary
interface to ERR_FATAL and ERR_NONFATAL
1– Enable the forwarding of secondary SERR# to
ERR_FATAL or ERR_NONFATAL.
ISA Enable – Modifies the response by the bridge to ISA I/O
addresses. This applies only to I/O addresses that are enabled by
the I/O Base and I/O Limit registers and are in the first 64 KB of
PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is
set, the bridge will block any forwarding from primary to
secondary of I/O transactions addressing the last 768 bytes in each
1-KB block. In the opposite direction (secondary to primary), I/O
transactions will be forwarded if they address the last 768 bytes in
each 1-KB block.
2
RW
0b
0 – Forward downstream all I/O addresses in the address
range defined by the I/O Base and I/O Limit registers.
1– Forward upstream ISA I/O addresses in the address
range defined by the I/O Base and I/O Limit registers that
are in the first 64 KB of PCI I/O address space (top 768
bytes of each 1-KB block).
VGA Enable (Optional) – Modifies the response of the bridge to
VGA-compatible addresses. If this bit is set, the bridge will
forward the following accesses on the primary interface to the
secondary interface (and, conversely, block the forwarding of these
addresses from the secondary to primary interface):
3
RW
0b
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