GL9701 PCI ExpressTM to PCI Bridge
Device Control register.
Fatal Error Detected – This bit indicates status of Fatal errors
detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
2
RW1C
0b
Unsupported Request Detected – This bit indicates that the
device received an Unsupported Request. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control register.
3
4
RW1C
RO
0b
0b
AUX Power Detected – Devices that require AUX power report
this bit as set if AUX power is detected by the device.
Transactions Pending – This bit when set indicates that the
device has issued Non-Posted Requests which have not been
completed. A device reports this bit cleared only when all
outstanding Non-Posted Requests have completed or have been
terminated by the Completion Timeout mechanism.
5
RO
0b
RsvdZ
15:6
RsvdZ
000h
6.32 Offset 7ch: PCI Express Link Capabilities Register
Bits
Type
Default
Description
Maximum Link Speed – This field indicates the maximum Link
3:0
RO
0001b speed of the given PCI Express Link. Defined encodings are:
0001b 2.5 Gb/s Link
Maximum Link Width – This field indicates the maximum width
of the given PCI Express Link.
9:4
RO
RO
RO
RO
00001b
00b
Active State Power Management (ASPM) Support –
Not supported
11:10
14:12
17:15
L0s Exit Latency – This field indicates the L0s exit latency for the
given PCI Express Link.
111b
111b
L1 Exit Latency – This field indicates the L1 exit latency for the
given PCI Express Link.
RsvdP
23:18
31:24
RsvdP
RO
00h
01h
Port Number – This field indicates the PCI Express Port
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