GL9701 PCI ExpressTM to PCI Bridge
0001b 2.5 Gb/s PCI Express Link
Negotiated Link Width – This field indicates the negotiated
9:4
10
RO
RO
000001b
0b
width of the given PCI Express Link.
Training Error – This read-only bit indicates that a Link training
error occurred.
Link Training – This read-only bit indicates that Link training is
in progress (Physical Layer LTSSM in Configuration or
Recovery state) or that 1b was written to the Retrain Link bit but
Link training has not yet begun. Hardware clears this bit once Link
training is complete.
11
RO
0b
Slot Clock Configuration – This bit indicates that the
component uses the same physical reference clock that the
platform provides on the connector.
12
RO
1b
RsvdZ
15:13
RsvdZ
000b
6.35 Offset 94h: PM Capability ID Register
Bits
Type
Default
Description
ID – This field, when “01h” identifies the linked list item as being
7:0
RO
01h
the PCI Power Management registers.
6.36 Offset 95h: PM Next Pointer Register
Bits
Type
Default
Description
7:0
RO
a0h
Next Item Pointer – Next capability is Slot Numbering capability.
6.37 Offset 96h: Power Management Capabilities Register
Bits
2:0
3
Type
Default
Description
Version – A value of 010b indicates that this function complies
RO
010b with Revision 1.1 of the PCI Power Management Interface
Specification.
PME Clock – Indicates that no PCI clock is required for the
RO
0b
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