GL9701 PCI ExpressTM to PCI Bridge
number for the given PCI Express Link.
6.33 Offset 80h: PCI Express Link Control Register
Bits
1:0
2
Type
RO
Default
00b
Description
Active State Power Management (ASPM) Control –
GL9701 does not support ASPM.
RsvdP
RsvdP
0b
Read Completion Boundary (RCB) – Indicates the RCB value
for the Root Port. Defined encodings are:
0b : 64 byte
3
RO
0b
1b : 128 byte
Link Disable – This bit disables the Link when set to 1b.
4
5
RW
RW
0b
0b
Retrain Link – A write of 1b to this bit initiates Link retraining by
directing the Physical Layer LTSSM to the Recovery state.
Common Clock Configuration – This bit when set indicates
that this component and the component at the opposite end of
this Link are operating with a distributed common reference clock.
A value of 0b indicates that this component and the component at
the opposite end of this Link are operating with asynchronous
reference clock.
6
RW
0b
Extended Synch – This bit when set forces the transmission of
4096 FTS ordered sets in the L0s state followed by a single SKP
ordered set prior to entering the L0 state, and the transmission of
1024 TS1 ordered sets in the L1 state prior to entering the
Recovery state.
7
RW
0b
RsvdP
15:8
RsvdP
00h
6.34 Offset 82h: PCI Express Link Status Register
Bits
Type
Default
Description
Link Speed – This field indicates the negotiated Link speed of the
3:0
RO
0h
given PCI Express Link.Defined encodings are:
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