GL9701 PCI ExpressTM to PCI Bridge
64-bit Indicator: These bits indicate that 64-bit addressing is not
19:16
31:20
RO
0b
supported for the limit.
Prefetchable Memory Limit: These bits are compared with
bits[31:20] of the incoming address to determine the upper 1
MB-aligned value (inclusive) of the range. The incoming address
must be less than this value.
RW
000h
6.20 Offset 28h: Prefetchable Base Upper 32-bits Register
Bits
Type
Default
Description
Prefetchable Memory Base Upper 32bit: These bits indicate that
31:0
RO
0000-0000h
full 64-bit addressing is not supported.
6.21 Offset 2ch: Prefetchable Limit Upper 32-bits Register
Bits
Type
Default
Description
Prefetchable Memory Limit Upper 32bit: These bits indicate
31:0
RO
0000-0000h
that full 64-bit addressing is not supported.
6.22 Offset 30h: IO Base and Limit Upper 16-bits Register
Bits
15:0
Type
RO
Default
0000h
0000h
Description
I/O Base Upper 16 Bits: 32-bit IO addressing is not supported
I/O Limit Upper 16 Bits: 32-bit IO addressing is not supported
31:16
RO
6.23 Offset 34h: Capabilities Pointer Register
Bits
Type
Default
Description
Capabilities Pointer: These bits indicate that the pointer for the
first entry in the capabilities list is at 70h in the configuration
space.
7:0
RO
70h
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