GL9701 PCI ExpressTM to PCI Bridge
6.24 Offset 3ch: Interrupt Line Register
Bits
Type
Default
Description
Interrupt Line: Used to communicate interrupt line routing
information. Software will write the routing information into this
register as it initializes and configures the system.
7:0
RW
00h
6.25 Offset 3dh: Interrupt Pin Register
Bits
Type
Default
Description
Interrupt Pin: GL9701 does not use an interrupt pin.
7:0
RO
00h
6.26 Offset 3eh: Bridge Control Register
Bits
Type
Default
Description
Parity Error Response Enable – Controls the bridge’s
response to uncorrectable address, attribute, and data errors on the
secondary interface.
0
RW
0b
0 – Ignore uncorrectable address, attribute, and data
errors on the secondary interface.
1 – Enable uncorrectable address, attribute, and data error
detection and reporting on the secondary interface.
SERR# Enable – Controls the forwarding of secondary interface
SERR# assertions to the primary interface. The bridge will
transmit an ERR_FATAL or ERR_NONFATAL cycle on the
primary interface when all of the following are true:
S ERR# is asserted on the secondary interface.
1
RW
0b
The SERR# Enable bit is set in the Command register or the PCI
Express-specific bits are set (refer to Chapter 10 for
details) in the Device Control register of the PCI Express
Capability Structure.
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