GL9701 PCI ExpressTM to PCI Bridge
Detected Parity Error – This bit reports the detection of an
uncorrectable address, attribute, or data error by the bridge on its
secondary interface.
The bit is set irrespective of the state of the Parity Error
Response Enable bit in the Bridge Control register.
0 – Uncorrectable address, attribute, or data error not
detected on secondary interface
15
RW1C
0b
1 – Uncorrectable address, attribute, or data error detected on
secondary interface
6.18 Offset 20h: Memory Base and Limit Register
Bits
Type
Default
Description
Reserved
3:0
RO
0h
Memory Base: These bits are compared with bits[31:20] of the
incoming address to determine the lower 1 MB-aligned value
(inclusive) of the range. The incoming address must be greater
than or equal to this value.
15:4
19:16
31:20
RW
RO
RW
000h
0h
Reserved
Memory Limit: These bits are compared with bits[31:20] of the
incoming address to determine the upper 1 MB-aligned value
(exclusive) of the range. The incoming address must be less than
this value.
000h
6.19 Offset 24h: Prefetchable Memory Base and Limit Register
Bits
Type
Default
Description
64-bit Indicator: These bits indicate that 64-bit addressing is not
supported for the base.
3:0
RO
0h
Prefetchable Memory Base: These bits are compared with
bits[31:20] of the incoming address to determine the lower 1
MB-aligned value (inclusive) of the range. The incoming address
must be greater than or equal to this value.
15:4
RW
000h
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 42
GENESYS [ GENESYS LOGIC ]
