GL9701 PCI ExpressTM to PCI Bridge
bit location. If the Parity Error Response Enable bit is set to zero,
this bit will not be set when an error is detected.
0 – No uncorrectable data error detected on the secondary
interface.
1 – Uncorrectable data error detected on the secondary
interface.
DEVSEL Timing – This bit field encodes the timing of the
secondary interface DEVSEL# as listed below.
00 – Fast DEVSEL# decoding
10:9
RO
01b
01 – Medium DEVSEL# decoding
10 – Slow DEVSEL# decoding
11 – Reserved
Signaled Target-Abort – This bit reports the signaling of a
Target-Abort termination by the bridge when it responds as the
target of a transaction on its secondary interface or when it signals
a PCI-X Split Completion with Target-Abort.
0 – Target-Abort not signaled on secondary interface.
1 – Target-Abort signaled on secondary interface.
Received Target-Abort – This bit reports the detection of a
Target-Abort termination by the bridge when it is the master of a
transaction on its secondary interface.
11
RW1C
0b
12
13
RW1C
RW1C
0b
0b
0 – Target-Abort not detected on secondary interface.
1 – Target-Abort detected on secondary interface.
Received Master-Abort – This bit reports the detection of a
Master-Abort termination by the bridge when it is the master of a
transaction on its secondary interface.
0 – Master-Abort not detected on secondary interface.
1 – Master-Abort detected on secondary interface.
Received System Error – This bit reports the detection of an
SERR# assertion on the secondary interface of the bridge.
0 – SERR# assertion on the secondary interface has not
been detected.
14
RW1C
0b
1 – SERR# assertion on the secondary interface has been
detected.
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 41
GENESYS [ GENESYS LOGIC ]
