GL9701 PCI ExpressTM to PCI Bridge
6.6 Offset 0ch: Cache Line Size Register
Bits
Type
Default
Description
Cache Line Size: Specifies the system cacheline size in units of
7:0
RW
00h
DWORDs.
6.7 Offset 0dh: Primary Latency Timer Register
Bits
Type
Default
Description
Primary Latency Timer: The primary/master latency timer does
7:0
RO
00h
not apply to PCI Express bridges..
6.8 Offset 0eh: Header Type Register
Bits
Type
Default
Description
Header Type: Indicates that the header is compatible with PCI
7:0
RO
01h
system software developed for Type 01h PCI and PCI-X bridges.
6.9 Offset 0fh: Bist Register
Bits
Type
Default
Description
7:0
RO
00h
BIST: GL9701 does not support BIST.
6.10 Offset 10h: Base Register0
Bits
Type
Default
Description
31:0
RO
00h
Base Register0: GL9701 does not use base register.
6.11 Offset 14h: Base Register1
Bits
Type
Default
Description
31:0
RO
00h
Base Register1: GL9701 does not use base register.
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