GL9701 PCI ExpressTM to PCI Bridge
Signaled System Error – This bit is set when the bridge sends an
ERR_FATAL or ERR_NONFATAL message to the Root
Complex and the SERR# Enable bit in the Command register is
set.
14
RW1C
0b
0 – Neither ERR_FATAL nor ERR_NONFATAL transmitted
on primary interface.
1 – ERR_FATAL or ERR_NONFATAL transmitted on
primary interface.
Detected Parity Error – This bit is set by the bridge whenever it
receives a poisoned TLP or, if supported, a TLP with bad ECRC
(Read Completion or Write Request) on the primary interface,
regardless of the state the Parity Error Response bit in the
Command register.
15
RW1C
0b
0 – Data poisoning and bad ECRC not detected by the
bridge on its primary interface.
1 – Data poisoning or bad ECRC detected by the bridge on its
primary interface.
6.4 Offset 08h: Revision ID
Bits
Type
Default
Description
7:0
RO
00h
Revision ID: Indicates the die version of GL9701.
6.5 Offset 09h: Class Code
Bits
Type
Default
Description
Programming Interface (PIF): This bit indicates that this device
is standard PCI-to-PCI Bridge.
7:0
RO
00h
Sub Class Code (SCC): This 8-bit value indicates that this device
is a PCI-to-PCI Bridge.
15:8
RO
RO
04h
06h
Base Class Code (BCC): The value of 06h indicates that this is a
bridge device.
23:16
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