GL9701 PCI ExpressTM to PCI Bridge
6.1 Offset 00h: Device Identification
Generic configuration software will be able to determine what devices are available on PCI bus via these
information. All of these registers are read-only.
Bits
15:0
Type
RO
Default
Description
17a0h Vendor ID: This field identifies the manufacturer of the device.
7163 Device ID: This field identifies the particular device.
31:16
RO
6.2 Offset 04h: Command Register
Bits
Type
Default
Description
I/O Space: Controls a device’s response to I/O Space accesses.
0– Disables the device response.
0
RW
0b
1– Allows the device torespond to I/O Space accesses.
Memory Space: Controls a device’s response to Memory Space
accesses.
1
RW
0b
0– Disables the device response.
1– Allows the device to respond to Memory Space accesses.
Bus Master: Controls a device’s ability to act as a master on the
PCI bus.
2
3
RW
RO
0b
0b
0– Disables the device from generating PCI accesses.
1– Allows the device to behave as a bus master.
Special Cycles: Does not apply to PCI Express Bridge.
Memory Write and Invalidate Enable: GL9701 does not
optionally promote Memory Write Requests to Memory Write
and Invalidate transactions on PCI.
4
5
RO
RO
0b
0b
VGA Palette Snoop: Does not apply to PCI Express bridges.
Parity Error Response:
Controls the bridge’s setting of the Master Data Parity Error bit in
the Status register in response to a received poisoned TLP from
PCI Express.
6
RW
0b
0 – Disables the setting of the Master Data Parity Error bit.
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