GL9701 PCI ExpressTM to PCI Bridge
1– Enables the setting of the Master Data Parity Error bit.
Reserved
7
RO
0b
SERR# Enable: This bit enables reporting of non-fatal and
fatal errors to the Root Complex. In addition, this bit enables
transmission by the primary interface of ERR_NONFATAL and
ERR_FATAL error messages on behalf of SERR# assertions
detected on the secondary interface. Note that errors are reported if
enabled either through this bit or through the PCI Express specific
bits in the Device Control register.
8
RW
0b
0 – Disable the reporting of bridge non-fatal errors and
fatal errors to the Root Complex.
1 – Enable the reporting of bridge non-fatal errors and fatal
errors to the Root Complex.
9
RO
0b
0b
Fast Back-to-Back Transactions Enable: Does not apply to PCI
Express bridges.
10
RW
Interrupt Disable: GL9701 does not generate INTx interrupt
messages on behalf of internal sources hence implements this bit as
read-only with a value of 0.
15:11
RO
00h
Reserved
6.3 Offset 06h: Status Register
Bits
Type Default
Description
2:0
3
RO
RO
0h
0b
Reserved
Interrupt Status – Indicates that an INTx interrupt message is
pending on behalf of sources internal to the bridge.
Capabilities List – Indicates the presence of a Capability List
item.
4
RO
1b
5
6
7
RO
RO
RO
0b
0b
0b
66 MHz Capable – Does not apply to PCI Express bridges.
Reserved
Fast Back-to-Back Transactions Capable – Does not apply to
PCI Express bridges.
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