GL9701 PCI ExpressTM to PCI Bridge
Master Data Parity Error – This bit is used to report the
detection of uncorrectable data errors by the bridge. This bit is set
if the Parity Error Response bit in the Command register is set and
either of the following two conditions occur:
8
RW1C
0b
1– Uncorrectable data error detected on the primary
interface.
DEVSEL# Timing – Does not apply to PCI Express bridges.
Must be hardwired to 00b.
10:9
RO
00b
Signaled Target-Abort – This bit is set when the bridge
generates a completion with Completer Abort Completion Status in
response to a request received on its primary interface.
0 – Completer Abort Completion not transmitted on the
primary interface.
11
RW1C
0b
1 – Completer Abort Completion transmitted on the primary
interface.
Received Target-Abort – This bit is set when the bridge
receives a Completion with Completer Abort Completion Status on
its primary interface.
12
RW1C
0b
0 – Completer Abort Completion Status not received on
primary interface.
1 – Completer Abort Completion Status received on primary
interface.
Received Master-Abort – This bit is set when the bridge
receives a Completion with Unsupported Request Completion
Status on its primary interface.
13
RW1C
0b
0 – Unsupported Request Completion Status not received on
primary interface.
1 – Unsupported Request Completion Status received on
primary interface.
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