Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead,
SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
8.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in
Section 15, “High-Speed Serial Interfaces (HSSI).”
8.3.2
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
Table 36 lists the SGMII SerDes reference clock AC requirements. Note that SD2_REF_CLK and
SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
Table 36. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical Max Units
Notes
t
REFCLK cycle time
—
—
10 (8)
—
—
ns
ps
1
REF
t
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
100
—
REFCJ
t
Phase jitter. Deviation in edge location with respect to mean edge
location
–50
—
50
ps
—
REFPJ
Note:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected through cfg_srds_sgmii_refclk during POR.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
FREESCALE [ Freescale ]
