Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 34. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
t
1.0
—
10.0
ns
RMTDX
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
MTX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
MTX
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 19 shows the RMII transmit AC timing diagram.
t
t
RMTR
RMT
TSECn_TX_CLK
t
t
RMTH
RMTF
TXD[1:0]
TX_EN
TX_ER
t
RMTDX
Figure 19. RMII Transmit AC Timing Diagram
8.2.7.2
RMII Receive AC Timing Specifications
Table 35 shows the RMII receive AC timing specifications.
Table 35. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition Symbol
TSECn_TX_CLK clock period
1
Min
Typ
Max
Unit
t
15.0
35
20.0
50
—
25.0
65
ns
%
RMR
TSECn_TX_CLK duty cycle
t
RMRH
TSECn_TX_CLK peak-to-peak jitter
Rise time TSECn_TX_CLK (20%–80%)
Fall time TSECn_TX_CLK (80%–20%)
t
—
250
2.0
2.0
—
ps
ns
ns
ns
RMRJ
t
1.0
1.0
4.0
—
RMRR
t
—
RMRF
RXD[1:0], CRS_DV, RX_ER setup time to
TSECn_TX_CLK rising edge
t
—
RMRDV
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
41
FREESCALE [ Freescale ]
