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MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC)  
8.3.4  
SGMII AC Timing Specifications  
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver  
characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver  
inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 25, respectively.  
8.3.4.1  
SGMII Transmit AC Timing Specifications  
Table 39 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.  
Table 39. SGMII Transmit AC Timing Specifications  
At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
Deterministic Jitter  
Total Jitter  
JD  
JT  
0.17  
0.35  
UI p-p  
UI p-p  
ps  
1
Unit Interval  
UI  
799.92  
50  
800  
800.08  
120  
V
V
fall time (80%-20%)  
rise time (20%-80%)  
tfall  
ps  
OD  
OD  
t
50  
120  
ps  
rise  
Notes:  
1. Each UI is 800 ps ± 100 ppm.  
8.3.4.2  
SGMII Receive AC Timing Specifications  
Table 40 provides the SGMII receive AC timing specifications. Source synchronous clocking is not  
supported. Clock is recovered from the data. Figure 24 shows the SGMII receiver input compliance mask  
eye diagram.  
Table 40. SGMII Receive AC Timing Specifications  
At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.  
Parameter  
Deterministic Jitter Tolerance  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
JD  
JDR  
JSIN  
JT  
0.37  
0.55  
0.1  
UI p-p  
UI p-p  
UI p-p  
UI p-p  
1
1
Combined Deterministic and Random Jitter Tolerance  
Sinusoidal Jitter Tolerance  
Total Jitter Tolerance  
1
0.65  
1
-12  
Bit Error Ratio  
BER  
UI  
10  
2
Unit Interval  
799.92  
5
800  
800.08  
200  
ps  
AC Coupling Capacitor  
C
nF  
3
TX  
Notes:  
1. Measured at receiver.  
2. Each UI is 800 ps ± 100 ppm.  
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.  
4. Refer to RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
Freescale Semiconductor  
47  
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