Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
MPC8572E SGMII
SerDes Interface
SD2_TXn
SD2_TXn
50 Ω
50
50
Ω
Transmitter
V
V
OD
os
50 Ω
Ω
Figure 23. SGMII Transmitter DC Measurement Circuit
Table 38 lists the SGMII DC receiver elecetrical characteristics.
Table 38. SGMII DC Receiver Electrical Characteristics
Parameter
Supply Voltage
Symbol
Min
Typ
Max
Unit
Notes
XV
1.045
1.1
N/A
—
1.155
V
—
—
1
DD_SRDS2
DC Input voltage range
Input differential voltage
—
LSTS = 0
LSTS = 1
LSTS = 0
LSTS = 1
V
100
175
30
1200
mV
2, 4
RX_DIFFp-p
—
Loss of signal threshold
VLOS
—
100
175
100
120
35
mV
3, 4
65
—
Input AC common mode voltage
V
—
mV
Ω
5
CM_ACp-p
Receiver differential input impedance
Z
80
20
100
—
—
—
RX_DIFF
Receiver common mode input
impedance
Z
Ω
RX_CM
Common mode input voltage
V
—
V
—
V
6
CM
xcorevss
Note:
1. Input must be externally AC-coupled.
2. V
is also referred to as peak to peak input differential voltage
RX_DIFFp-p
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to
PCI Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The LSTS shown in the table refers to the LSTSAB or LSTSEF bit field of MPC8572E’s SerDes 2 Control Register.
5. V
is also referred to as peak to peak AC common mode voltage.
CM_ACp-p
6. On-chip termination to SGND_SRDS2 (xcorevss).
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
46
FREESCALE [ Freescale ]
